Sr. FPGA Engineer
Coordinated every aspects of engineering design and development of Achieva's products, 1G/2G Fiber Channel Controller and 4G Fiber Channel Controllers right from architecture and specs finalization to ASIC tape-out. Responsible for complete ASIC development and deliverables, right from architecture and specs finalization to ASIC bring-up. Also responsible for leading Software.
- Architected, Designed, verified and Single handedly developed the 1G/2G Fiber Channel Controller, which provides 1G/2G Fibre channel FC-1 and FC-2 layer functions. Fibre Channel Controller is a single chip storage area network solution for host bus adapters with full Fibre channel support.
- Responsible for complete IP development and deliverables, right from architecture and specs finalization to FPGA proto-type targeted on Xilinx Virtex-II Pro, including Architecture, Functional Specs Documentation, Architecture documentation, RTL design doc, Micro-architecture, RTL, STA, Simulations, Synthesis, and bring-up.
- Achieved success in releasing deliverables while meeting time, cost, scope, and quality.
- Established Design process and Methodology for development of Fiber Channel MACs.
- Successfully architected Fiber Channel MAC.
- Substantial hands-on contributions to the product with direct ownership of various architectural, implementation, and ongoing support issues.
- Strong hands-on experience in RTL coding using Verilog HDL, STA, DFT/ATPG, Synthesis, Simulations, and Lab testing.
- Successfully managed concurrent multi-projects and experienced in multi-tasking.
- Managed remote/overseas (India) engineering teams.