Asic Engineer Resume Samples

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ASIC Engineers play a crucial role in verification teams and complete tasks such as deploying verification models, coordinating verification activities, developing support software, and integrating verification environments. Based on our most successful resume examples, these experts should showcase in their resumes computer systems expertise, problem solving orientation, attention to details, teamwork, and time management. Employers select candidates making display of a Bachelor's or Master's Degree in a relevant field in their resume (information technology or computer science preferred).

1

Petaluma, ASIC Engineer

Developed chip-level and block-level verification environments for 2nd generation Gigabit routing and cross connect ASIC using Verisity Specman.

  • Developed verification environments for various "Gigabit routing and cross connect ASIC" modules such as Framer, Media Access Control, Scrambler, SERDES, and Frame Aligner. Also wrote verification plan and developed directed and random tests. All the tests were self checking. The checking was done using scoreboard and reference models.
  • Developed functional verification environment for DS3 mapper ASIC using Verisity Specman. Wrote verification plan and developed directed and random tests. All the tests were self checking. The checking was done using scoreboard and reference models.
  • Extracted and analyzed coverage data using Surecov tool.
  • Developed regression and post processing automation scripts using Perl.
  • Developed chip-level verification environment and performed verification for 1st generation Gigabit routing and cross connect ASIC using Verisity Specman.
Candidate Info
13
years in
workforce
2
years
at this job
Bsee
2

ASIC Engineer

Worked and made solid contributions to a SSD SoC project. Specific duties included: RTL based hardware design in Verilog, large scale logic synthesis, low power implementation and verification, static timing analysis, and formal verification using Synopsys and Cadence EDA tools. Came up to speed very quickly on using the new EDA tools.

  • Extensively used Perl and TCL programming languages to drive the tools as well as UPF and CPF development for power island implementation.
  • Collaborated with the verification team to execute directed test simulations using System Verilog and VMM for the SSD SoC projects.
  • Collaborated with the verification team to prepare MVSIM verification plan, compiled the flow to integrate UPF with MVSIM and ran MVSIM to dynamically verify power-managed multi-voltage SoC designs.
Candidate Info
9
years in
workforce
5
years
at this job
3

Asic Engineer

Key contributor to the development of three ASIC chips, two of which went into production in 65nm TSMC LP process, and the third, in 40nm TSMC process, is awaiting customer approval for test parts.

  • Main designer of a CPU subsystem which consisted of integrating a Synopsys ARC601 CPU, a HDMI 1.4 interface IP, SRAM, an I2C interface, an AES decryption module, a SPI controller, and a video upscaler on an AHB bus. Wrote interfaces using Verilog RTL so that all modules were able to seamlessly operate together on the AHB bus to form a fully functional system. Wrote Verilog testbenches to verify the entire subsystem which has been fully functional and extensively used on two production ASICs.
  • Implemented a major 2 million-gate video noise reduction module in Verilog RTL. Individual submodules were coded in Verilog RTL; subsystems were verified against C models; and each block was synthesized using Synopsys Design Compiler.
  • Implemented a gamma correction module. The module was synthesized and integrated into the video data path of three ASICs.
  • Performed static timing analysis on an 8 million-gate, 8 clock domain, ASIC using Synopsys PrimeTime.
  • Performed equivalence checking on various submodules using Synopsys Formality.
  • Performed ECOs on post layout netlists to do metal layer bug fixes.
Candidate Info
12
years in
workforce
4
years
at this job
BS
Mechanical Engineering
MS
Electrical Engineering
4

ASIC Engineer

Performed design changes and developed test-benches on the Buffer Manager, Disk Formatter, Servo, and Signal Pulse Generator blocks on a customer's ASIC

  • Participated in the design of a full chip test bench suite to validate the operation of the customer's ASIC
  • Developed behavioral code and test benches for the design and verification of the Serial ATA module
  • Implemented RCS for revision control to checkpoint design files
Candidate Info
8
months in
workforce
8
months
at this job
BS
Electrical Engineering
5

Senior Digital ASIC Engineer

Responsible for the specification, design, and verification of digital logic implemented in ASICs and/or FPGAs for use in wireless communication systems. Participated in the evaluation and recommendation of design tools for use in the ASIC design and verification process. Designs were done in VHDL, Verilog, and SystemVerilog.

  • Participated in the specification, design, and verification of chips used in IEEE 802.11 wireless systems. Design assignments included clock recovery logic, content-addressable lookup, binary search engine, ethernet remote monitoring (RMON MIB, RFC 2819), JTAG (IEEE 1149.1) boundary scan, and interfaces to various external devices. The chips went into production with no re-spins and have been used in numerous wireless products.
  • Collaborated with design groups in remote locations, which required accurate communication and coordination of efforts. Achieved seamless integration between modules designed in different locations.
  • Assisted in the development of standard documentation templates, design and verification procedures, and various tool usage tutorials providing a documented design process in compliance with ISO 9000. Several of the items developed were considered "best practices" within Cisco.
  • Maintained the tools, licenses, and libraries used by the ASIC group. Adapted and maintained a wrapper system, allowing team members access to all ASIC tools without exceeding the limits of various system variables. This also enabled all users to utilize the same, latest versions of the tools, thereby reducing errors caused by using conflicting tool versions.
  • Created a method to automatically update the list of valid license servers for each tool, thus preventing tool errors due to incorrect LICENSE paths.
Candidate Info
10
years in
workforce
10
years
at this job
BS
Electrical Engineering
6

Senior ASIC Engineer

Carried out design, RTL coding, simulation, synthesis, timing check, system integration, and test case functions, ensuring compliance with unified test plan, as part of basic design flow responsibilities.

  • Communicated closely with senior engineers for technical design and applications for new designs.
  • Conduct whole chip synthesis, debugging and test vector generation for production.
  • Performed all design flow activities for VersiCore project, targeting reusability in general bus architecture. Project involved RISC CPU core, general bus structure, RTL coding, and front end design work.
Candidate Info
19
years in
workforce
11
years
at this job
BS
Bachelor of Science
7

ASIC Engineer

Micro-architecture design, RTL coding for I2C and Vedio blocks for Trimedia graphic multimedia processor chips.

  • SOC integration for DFT logic including scan chain, MBIST and JTAG logic.
  • Performed Verplex equivalence check, ATPG and static timing analysis.
  • Supported tape out activity and gate level simulation with SDF back annotation. Silicon brings up and debug in ATE and lab.
Candidate Info
4
years in
workforce
4
years
at this job
BS
Project Management, Uc Santa Cruz Ext
MS
Master of Science
MS
Design
8

Principal ASIC Engineer

Responsible for the architecture and design for MAC_PHY interface of 802.15a Phy and MBOA MAC.

  • Architected and designed control logic for the Transmit and Receive chains of the base band design running at 533 Mhz.
  • Integrated the Receive and Transmit chains of the base band.
  • Architected and designed various blocks of the base band. These included but were not limited to Interleaver, deinterleaver, modulator, demodulator, puncterer, depuncturer, channel estimation, phase equalization, time drift, encoder, all running at 533 Mhz.
  • Worked closely with several comm. System Engineers to perform cycle accurate validation of various Physical layer RTL designs with fixed point C models.
  • Responsible for designing the base band, Radio interface.
Candidate Info
13
years in
workforce
2
years
at this job
Msee
9

ASIC Engineer

Facilitated customer completion of all requirements of [company name] methodology prior to release to manufacturing of customer designs. Handled customer and [company name] Team inquiries.

  • Provided customer with DRC/LVS/RC extraction and simulation, as well as IP testing and mixed signal testcase development, supporting customer integration and improving time to market of parts.
  • Taught customers to use [company name] IO Scan Insertion tools, Insert [company name] or IEEE 1149.1 boundary scan, IO padring into the design top level, while facilitating pin sharing, improving customer satisfaction.
  • Taught customers to use Netlist Processing tools, convert flip flops to scan latches ([company name] LSSD), and perform [company name] scan chain balancing.
  • Clock Tree Creation and Insertion tools, creation of functional clocks.
  • Static Timing, Debug timing assertions and help them close, timing.
Candidate Info
4
years in
workforce
4
years
at this job
BS
Electrical Engineering
10

Senior ASIC Engineer

Member of the ASIC team that designed RAID controllers, SCSI, and SATA host bus adapters. Responsibilities included ASIC design conception and enhancements to increase performance and reduce cost of the PCB's.

  • Developed Verilog bus functional compliance models for use with an internal proprietary bus interface. The models were adapted for use throughout the company.
  • Designed multiple generations of RAID DMA engines. The result was an increase in performance of the RAID controllers.
  • Designed memory (EDO DRAM, SDRAM and FLASH) controllers.
  • Created VHDL ASIC simulation model for use with system testing.
  • Generated test and functional vectors for ASIC's. This included test software written in C to verify operation of embedded processors and SCSI cores.
  • Performed PCI bus compliance testing.
  • Designed JTAG controllers and I/O interface logic.
Candidate Info
20
years in
workforce
10
years
at this job
BS
Physics
BA
Bachelor of Arts
MA
Master of Arts

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