Senior ASIC Verification Engineer
Lead design verification of NAND flash memory controller SoCs used in Sandisk's flash memory cards and SSDs.
- Created comprehensive verification plan and strategy for on-time delivery of high quality SoCs. Developed and managed verification schedules, milestones and deliverables according to the project's requirements.
- Managed a global team of 4 to 8 verification engineers for each project.
- Executed verification plan from inception to completion making sure it achieved 100% code coverage.
- Interfaced with cross-functional teams (Design, Verification, FPGA, Physical Design and Firmware) to resolve any issues blocking product delivery.
- On top of planning and leading verification effort, performed hands on coding, debugging, test plan development and test automation.
- All issues found during verification were tracked to completion using JIRA issue tracker tool.
- Made sure the project is verified to the highest quality standards by driving the team to use best in class verification methods and tools through evaluation and deployment of new vendor tools and products.
- Hired and mentored new team members.
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Product Verification Engineer
Perform product test verification for CDG1 & CDG2 lab entry criteria for IS95 and CDMA2000 mobile handsets.
- Performed testing for CDG2 that met entrance criteria for IOT and CTIA Labs test certifications.
- Developed and Executed Test plans that identified and troubleshot issues before lab entry submittals or during product customer acceptance, including CTIA, FCC/IC, NAL for China Unicom and ANATEL for Vivo in Brazil.
- Utilized standard reports (Engineering and Factory) to provide feedback to R&D programs to resolve any open issues.
- Implemented and tested Audio/Acoustic.
- Optimized rack performance by eliminating calibration failures and increasing measurements accuracy.
- Correlated test equipment and requirements with external Labs such as Verizon, Sprint, Alltel and USCellular among others, resulting in more reliable results.
- Instructor at Electronic Engineering School for the following subjects, Engineering Circuit Analysis, Calculus and Autocad Rel. 12.
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Design Verification Engineer
- Volunteered to take ownership in creating a pre-Si verification environment, using C++, for an Intel IP codename Crystal Beach DMA engine (v1.1), one of the major block for the project Clarksboro.
- Re-designed the CBDMA verification environment for Tylersburg project to support the updated version 3.3
- Wrote verification test plans for both Clarksboro and Tylersburg projects
- Mentored a junior engineer during the pre-A0 milestone of Tylersburg
- Volunteered to help out in reproducing the 3 critical design bugs found by post-Si team affecting another Intel IP (VT-d, Virtualization Technology for Directed I/O) block. The expedited works in reproduction of the bugs helped the company to avoid a delay in PRQ.
- Joined Jaketown at a later stage of the project, created a Perl script to generate test patterns for CBDMA for use in the emulation environment to fill up a coverage
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Senior Systems Engineer (project Systems Engineer and System Integration / Verification Engineer)
Systems engineering and subsequent system verification of the Cougar advanced, multi-rack, shelterized signal processor sub-element.
- LabVIEW and LabWindows (writing C code) to automate RF/IF test equipment control and data collection (Spectrum Analyzers, Arbitrary Waveform Generators, Oscilloscopes, Power Meters, Frequency Counters).
- Wrote test plans, integration procedures, and design verification procedures.
- Developed and performed the design verification procedures for the Signal Acquisition and Simulation test cases.
- Integrated software threads with hardware.
- Allocated system specifications to Integrated Product Teams (IPTs).
- Created MS Access database to track sub-element requirements and issues. This data was used in preparation of Preliminary Design Review (PDR) and Critical Design Review (CDR) charts, incorporated into Sub-System Design Documents, use-case, test plan, and test procedure documents.
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