- Featured in:
More Fpga Design Engineer Resumes
Use these Fpga Design Engineer samples as a guideline or visit our extensive library of customizable resume templates.
High Quality
The best examples from thousands of real-world resumes
Expert Approved
Handpicked by resume experts based on rigorous standards
Diverse Examples
Tailored for various backgrounds and experience levels
Additional Engineering Resume Samples
Fpga Design Engineer Resume Samples
No results found
0-5 years of experience
Architected and implemented the on-chip memory interconnect for Convey's MX (large memory) coprocessor, balancing system performance with area utilization.
- Developed application specific Xilinx Virtex5/6 FPGA builds ("personalities") that accelerated customer applications on Convey's high memory bandwidth coprocessor.
- Designed components of a Vector Personality Development Kit ("VPDK") that allowed multiple vector applications to be quickly and easily implemented on Convey systems.
- Created an abstraction layer for the VPDK framework that gave the customer dynamic control over the vector design and created an encapsulated Black Box where the customer could place their highly sensitive IP without having to expose it.
- Hold a current Government Security Clearance.
0-5 years of experience
FPGA architecture and design for [company name]'s variety of 40GE, 10GE and 1GE load modules.
- Worked on wide variety of Xilinx FPGA from Spartan-2 to Virtex-5.
- Developed and enhanced IP cores for memory controller, Network interface, Microcontroller interface, Checksum Engines, SERDES, etc.
- Consistently worked on debugging and troubleshooting issues affecting product level.
- Investigated and resolved customer issues independently.
0-5 years of experience
Lead implementation designer of ethernet over SONET and ethernet adaption family of cost reduced solutions in FlashWave series of optical products implemented in Xilinx Virtex 4/5 families.
- Completed RTL implementation, timing improvement of top level and SONET_FRAMER.
- Undertook FPGA device evaluation and selection.
- Completed user timing constraints. Developed and organized scripts, Makefiles for black box, compile point synthesis for process efficiency.
- Integrated partitions for reuse blocks.Designed chip floorplan in Planahead for timing closure.
- Interfaced with cross functional teams and successfully resolved issues in pre/post routed designs. Implemented constraint changes/hand edits using FPGA editor to complete the design for critical customer releases.
- Completed RTL design, integration, and verification of SONET_FRAMER.
- Completed comprehensive chip synthesis, STA constraints. Improved timing margins.
- Co-ordinated with cross functional teams and successfully resolved all outstanding SERDES, IP, hardware, software issues.
- Managed floorplanning including clock tree design, ATPG, Boundary Scan, Power Management and ECO.
0-5 years of experience
Architected FPGA hosting a 4K120 video path that includes DipslayPort 1.2 multi-streaming inputs, 4K up and down scalers, frame rate converters, a PCIe streaming frame capture subsystem, and a Vx1 output to the panel.
- Designed and implemented a clock recovery subsystem for DisplayPort inputs.
- Managed consulting groups, including Bitec and Omnitek.
- Worked closely with GPU vendors AMD and nVidia.
6-10 years of experience
Design engineering and technical support for ground support equipment (GSE) used on several space and military programs. Responsibilities include: design and test of equipment used to test and troubleshoot system operations in various development stages. Author of various test procedures as well as several failure modes analysis documents. Expertise in FPGA design and development as well as upgrades to existing FPGA designs.
- Designated FPGA design lead for Orion Phased Array Antenna (PAA) Program. Lead FPGA designer responsible for VHDL code design in an Actel PROASIC 3 device. FPGA design requirements included: Manchester encoded serial interface to host, Telemetry operations, Parallel in serial operations to system shift registers, Automatic level control, EEPROM interface, and Built in Test. Specific VHDL design responsibilities included: Telemetry operations (ADC reads and temporary storage of data), Parallel in / serial out operations, command interface and telemetry operations. As the lead FPGA designer, responsibilities included knowledge of all FPGA module designs and their functionality and that FPGA functions addressed all customer and internally derived requirements. Insured that FPGA design followed Ball Aerospace FPGA work instruction guidelines, including assurance that all documents were adequately completed, and all formal peer reviews of documents were scheduled and completed. As a lead FPGA designer direct interaction with various mechanical/electrical and system engineers was required. Responsible for critical design review presentation for customer.
- Critical member of a multi-disciplined engineering team responsible for VHDL code design for a High Accuracy Star Tracker. Targeted device: ACTEL RTAX2000 FPGA. Design responsibilities for command, telemetry and pixel interface between system electronics and star tracker head. VHDL design included power and heater relay control, various time stamp operations and multiple interfaces to embedded block ram for system access and storage.
- Member of a 2-engineer design team responsible for the design and development of a flash LADAR 3D imaging system. Responsible for board level design, layout and operatonal testing of the electronics hardware. As the responsible engineer for the board design, oversaw a subcontractor designated to produce drawings, layout board and assemble board. Also, directed this subcontractor in the hardware qualification. Completed high-level FPGA design for IRIG, cameralink and SDRAM interfaces and varying degrees of system operations.
- Lead electronics engineer responsible for system control and power distribution design for 6th generation LADAR system. Responsible engineer for all facets of this design, working with various technical disaplines and divisions within the company to complete the deliverable system.
- Designed high level mathematical curve fitting algorithims for higher LADAR system range accuracy using VHDL cores and FPGA fabric. Design consisted of multiple stages including multiplication, summing and division that acquired 4 sets of raw LADAR input data and pipelined each section through the curve fit process.
- Integral part of engineering team tasked to design multiple FPGA-based imaging systems. Responsible for a number of the sub-system designs, detailed FPGA design and hardware board level design. Xilinx Virtex-5, Virtex-4, and Virtex-2 Pro designs incorporated embedded PowerPC, microblaze processors, 1.06 Gbit/sec fibre channel interface, DDR SDRAM video frame buffers, closed loop motor controllers, serial ADC/DAC interfaces, USB 2.0 and DSP functions.
0-5 years of experience
- Architected and designed major sections of large ASICs including Verilog source, synthesis, testing, and integration. Coordinated work of several engineers.
- Verified operation of very complex Sonet/SDH and 10GE network communications ASICs using mixed VHDL/Specman-e co-simulation. This new flow increased ability to find problems and speed up testing.
- Developed FPGAs to test ASICs. This was needed for hardware debugging and firmware development.
0-5 years of experience
Developed NSA Suite B Crypto Engine Embedded with Diamond 106micro in Xilinx Virtex 6
- Developed HDL that utilized Xilinx PCIe core & Intelliprop Sata Bridge core for Cyber collection in Virtex 5
- Developed HDL that used in Next Generation sATCOM Terminal in Xilinx Virtex 5
- Re-Targeted a UDP based core from Xilinx Virtex 6 to Xilinx Virtex 7
- Developed & Integrated Imaging algorithm targeted for Xilinx Zynq-7000
- Developed Control System targeted for Xilinx Virtex 7 using ADC & DAC
0-5 years of experience
Ownership of digital hardware domain responsibilities, integration of DSP/networking IPs for high-speed low-latency communication
- Responsible for developing and testing lock-in amplifiers, PLLs, IIR filters in Verilog for implementing controller architecture.
- Developing firmware to communicate between ARM processor and programmable logic on the Zynq All-programmable SOC.
- Wrote socket programming in Java and C to enable TCPI/IP communication from PC client to FPGA server
- Performed and validated BERT tests with near end PCS/PMA loopback for testing transceivers on the ZC-706.
0-5 years of experience
- Responsible for enhancement and maintenance of FPGA and CPLD firmware for 4 different variants of Supervisory Control and High-Speed Data Acquisition devices for a client in the power quality monitoring industry
- Behavioral and VHDL RTL description of digital circuits and functional simulation through test-benches
- Provided solutions through FPGA to various PCB related issues
- Involved in synthesis, place and route and ensuring timing closure for the designs
- Performed functional verification and design modifications in the gain switching part of a signal processing module implemented on Xilinx Spartan-3 FPGA for the samples acquired from a bipolar ADC. The processing included 2’s complement – binary – 32 bit floating point conversion, gain switching, gain multiplication and offset correction for the acquired ADC samples.
- Enhancements to the module which performs continuous calibration on the FPGA’s internal clock to meet data sampling rate accuracy of 10 us. External time sources like GPS, RTC and IRIG-B used for clock drift management.
0-5 years of experience
GS Communications Systems _ Active security clearance. Participated in the design and development of tactical software radios for various military platforms. Also, designed and simulated FPGAs for cryptographic and Information Assurance subsystems.
- Developed RTL coding in VHDL, conducted verification with Modelsim, coded test -benches and procedure packages, synthesis with Synplify Pro and place & route with Quartus II (Stratix II, Cyclone III) and Xilinx ISE (Virtex) in a collaborative enterprise work environment. Implemented FIR, IIR and CIC filters and DSP communication algorithms in FPGAs developed with Catapult C and Matlab and familiar with System Verilog.
- Developed Test plans and testcases in the verification of top as well as lower level blocks that cross referenced requirements in a traceability matrix. Verified Ethernet packets and other communication protocols as well as security algorithms.
- Conducted Requirements capture and peer review, and developed technical documentation, design verification, and test specification.
0-5 years of experience
Architecture of control plane and data-path FPGAs for port adapters and linecards with 100-Mbit, 1-Gbit and 10-Gbit Ethernet ports.
- Verilog RTL coding, Synthesis, Placement & Routing and FPGA bit-file generation.
- Wrote Perl scripts for compiling, simulating and parsing result files.
- Wrote verification environments and test cases in Vera language.
- Worked with diagnostics and software teams to bring up and validate boards in the lab.
- Debugged, root-caused and fixed failures.
6-10 years of experience
Contribute to Post Production editor and video broadcast hardware development.
- Duties included design specification, device pin out, top level integration, design specification for the relevant block, micro-architecture of the block, design implementation using RTL coding techniques, Synthesis, place and route and timing sign off.
- Participated as member of the verification team.
- Interaction with 3rd party IP vendors with respect to front end design, timing views, and associated integration of (NIOS II, SERDES, DDR2/3 memory PHY/controller, PCIe core).
- Closely interfaced with various department engineers from design to field support.
10+ years of experience
Performed chip synthesis with Synopsys Design Compiler on multiple ASIC's (> 6 million gates)
- Performed chip static timing analysis (STA) using Synopsys PrimeTime on multiple ASIC's for timing constraint verification and final artwork release timing signoff
- Project lead responsible for technical liaison with vendor, oversight and resolution of all program technical issues as well as tracking of readiness for all technical milestones on two ASICs
- Designed and leveraged pen fire control, ADC measurement control and pixel data image processing blocks across several ASIC's, including design, integration, simulation, documentation and silicon verification
- Designed and implemented simulation testbench suites for many components in multiple inkjet ASIC's
- Integrated and verified various HDL IP, including a Vivante 3D/2D GPU, two vendor supplied ADCs and multiple Denali DDR2 memory controllers
- Owned DRAM system and component level timing analysis, timing closure activities and final timing signoff for multiple SDRAM, DDR1 and DDR2 designs
- Owned logical equivalence checking (LEC) using Cadence Conformal on a 6.8 million gate ASIC including debug and resolution of inequivalences
- Mentored other engineers in synthesis, STA and timing constraint generation, debug and verification
- Architected, implemented and verified novel modular pen data control block to support 20 inch wide page inkjet printing at 800 feet/minute using a Xilinx Virtex-6 FPGA while on loan to another HP division
0-5 years of experience
Line Size Expension 100BaseT Daughter Board (TDM Base Voice Module)
- Implemented 25MHz PCM to IP interface module
- Used Verilog/Sinplicity/Xilinx ISE to implement the design in Xilinx XCV150 device
- Utilized Verilog and Verilog-XL for creating verification testbenches and simulations
- Use Altera CPLD/Max+II and Verilog to design a Microprocessor to ASIC/FPGA configuration interface
- Created board level simulation environment of the design
- Used Synopsys smart models and Verilog-XL for creating verification testbenches
6-10 years of experience
FPGA design lead for various projects, responsible for architecture, requirements, design, simulation, test, hardware integration/debug, and document writing & reviewing
- Worked heavily with storage devices and storage protocols such as ATA & SATA, high speed interfaces, algorithm development
- Implemented XTS-256 encryption algorithm for a new product
- Design for performance by squeezing device timing to increase clock speed
- Extensive experience performing lab debug of software and hardware problems
- Fail-Safe Design Analysis (FSDA) concepts for high assurance/reliability
- Wrote software for releasable projects as well as for test and debug purposes
- Performed project engineer roles, system design, customer support/interface, new product integration
- Was a critical team member in taking a new product through NSA Type-1 certification
0-5 years of experience
Design Engineer
- VHDL Designer
- Developed ADSL ATM based transmitter targeting Altera FPGA
- Developed shock proof portable test system for customer premise testing
- Organized and managed test system for first generation ADSL equipment
6-10 years of experience
Designed and verified VHDL modules for an 8G Fibre Channel Load Tester (worked with a team, Xilinx Virtex 5, max clock frequency = 212.5 Mhz).
- Designed and verified VHDL modules for a 10G Ethernet Load Tester (worked with a team, Xilinx Virtex 5, max clock frequency = 219 Mhz).
- Designed and verified Verilog modules for a GEN3 PCI Express protocol analyzer (worked with a team, Altera Statix 5, max clock frequency = 250 Mhz).
- Designed and verified the complete FPGA for the 16G Fibre Channel Load Tester on x1k and x5k platforms (was solely responsible for the project, Altera Stratix 4, max clock frequency = 212.5 Mhz).
6-10 years of experience
- Implemented a baseband processor for a multi-rate BPSK receiver for use in an orbital vehicle; the design, based on a software simulation model, performed a suite of operations including FIR filtering, Doppler compensation, decimation filtering, phase alignment, as well as control/programming/management of peripheral devices (ADC, PLL, VGA, mixer, flash, etc.) over SPI interface.
- Designed a FPGA-based, all-in-one network switch firmware for orbital flight vehicle hardware. The design included data packet processing for UDP (IPv4) packets to handle command/telemetry across 24 channels. Other responsibilities included test bench verification, hardware bring-up/debug, system integration testing, production test & qualification of the network switch.
- Devised and implemented a fault tolerant, triple-redundant synchronization algorithm for deployment in remote vehicle maneuver control panel for use aboard the International Space Station.
- Developed a methodology for code-based implementation of triple modular redundancy; the scheme generates register logic elements operating on 3-way voting logic; performed radiation testing on test designs to measure performance improvement in radiation-induced functional interrupts
- Implemented a prototype SOQPSK radio using a software-defined radio platform; wrote custom code blocks in C++ to perform differential encoding/decoding, pulse shaping, baseband waveform generation, symbol timing recovery, phase detection and trellis decoding.
- Designed custom, PLB-bus-compatible IP peripherals for use in processor-based FPGA
- Wrote embedded test software for design verification and characterization of flight hardware.
0-5 years of experience
RTL development of FPGAs in the field of video streaming and data processing beginning from the architectural stage, through the RTL block writing, simulation and synthesis stages and up until the lab support stage.
- Extensive understanding of the integration and timing closure requirements for various design types.
- Working with diverse data protocols such as AVALON-ST or I2C.
- RTL development of a video streaming design block which requires multiple and interdependent outputs.
10+ years of experience
Lead FPGA Design Engineer on GPS Anti-Jam Receivers and other GPS related systems (more than six separate design efforts)
- Designs typically include: DSP EMIF, high performance filters (STAP algorithms), code generators, built-in-test functionality, serial communication interfaces (SPI and others)
- Manage entire design process including: requirements capture, design implementation, verification, timing closure, integration/test and design release
- Document all development phases in the "FPGA/ASIC Design Implementation Guide" ([company name] FPGA/ASIC design capture document)
- Perform verification of GPS Anti-Jam FPGA Designs
- Design of self-checking test benches with DSP/SW interface emulation, interfering signal stimulus, and closed loop signal processing
- Conduct code linting analysis and subsequent code clean-up
- Perform code coverage/test grading analysis to comply with DO-254 coverage metrics
- Perform traceability between requirements, test cases, and test benches
- Develop FPGA/system sizing estimates for future designs and R&D efforts
- Complete detailed FPGA pricing and scheduling reports for bids and proposals
0-5 years of experience
- Designed FPGA RTL code which interacted with Python software
- Debugged hardware / software interface issues by creating unit tests and integration tests
- Led all aspects of FPGA hardware development and test for radar environment simulator project
- Extensive lab test / debug experience using lab test equipment
- Developed I/O interfaces for components connected to FPGA such as ADC, DAC, and busses
- Implemented designs from system level specifications
- Simulation and board level test using Xilinx ISIM, Chipscope, and lab test equipment
0-5 years of experience
Developed and designed Altera Cyclone IV GXB FPGA system in Quartus II environment for RF Radio Transceiver with high speed LVDS RFCB (RF Control Bus) interface.
- Created NIOS II, code memory, FLASH, SPI, USB and I/O interfaces with Avalon bus in SOPC Builder.
- Generated new interfaces in Component Editor.
- Wrote VHDL, Test Bench and TCL scripts for simulation in ModelSim.
- Debugged the design in real time using USB-Blaster with SignalTap and EDS debugger.
- Wrote operating system, control and monitoring 'C' functions and routines in EDS environment for NIOS II processor.
- Generated HAL API BSF and FLASH programming files from sof.
- Created interrupt routines in 'C' and wrote related VHDL hardware.
- Programmed EPCS using synthesis sof and jic outputs, SFL and Quartus programmer.
- Designed and developed SLS USB using UTMI and ULPI interface.
- Designed FPGA schematic in PADS.
6-10 years of experience
FPGA implementations of HPC (High-Performance Computing) applications requiring high-speed, low-latency, host
communications, external memory support, and reconfiguration. Responsible for management and oversight of all
hardware and software development activity.
- PCI Express Gen2 and Gen3 x8 Application and Transaction Layer processing blocks.
- Multi-mode DMA Engine incorporating Scatter/Gather and strided block transfer capabilities.
- DDR/DDR2/DDR3 DRAM, RLDRAM, and QDR memory interfaces.
- Infrastructure for automated hardware integration of output from commercially available C-to-HDL compilers.
- Fast, space-efficient, hardware implementations of cryptographic functions, including AES, SHA, and HMAC.
- High-speed implementation of functionally augmented math operations using Xilinx gate-level primitives.
- Hardware tuning algorithms for calibration of high-speed source synchronous data capture using Xilinx
- Scripted chip-level auto-regressing verification suites.
- Scripted build environment to support numerous functional variants.
- Lead developer for chip-level synthesis, place-and-route, and timing closure (200 to 400 MHz core logic).
0-5 years of experience
Multiple processor connected RAM access control design for routing machine in Verilog.
- ARM and PowerPC processor based experience, such as FSM controller for the router.
- Design circuits using ModelSim, Xilinx ISE, and FPGA-embedded processors.
- Designing test programs for the ATE machine based functional, assertion and burn in test.
0-5 years of experience
- FPGA to ASIC Conversion for Loral's current generation (Omega 2) Satellite Control Electronics Unit (SCE) Telemetry Encoder module. Converted schematics into Verilog RTL and created Simulation and ATE testbenches.
- Design and Development (Verilog RTL) of Telemetry Encoder ASIC/FPGA for Loral's next generation (Omega 3) SCE. This design provides CCSDS frame format and sub-carrier waveform generation with BPSK modulation. Designed NCO module using a micro-controller, to allow for maximum configurability. Designed Configuration Module, where all registers are implemented via a single linear array to avoid multiple instantiations; address decoding via case statement, steers the data. Designed Configuration PROM I/F Module, where data download format includes CRC to ensure data integrity. Wrote Tcl script which extracts Memory Map tables from specification document, and directly modifies Configuration Module Verilog RTL (case statement conditions) to generate register decode tables.
- Helped maintain CVS Repository and Workstation Cygwin for various projects.
0-5 years of experience
- FPGA to ASIC Conversion for Loral's current generation (Omega 2) Satellite Control Electronics Unit (SCE) Telemetry Encoder module. Converted schematics into Verilog RTL and created Simulation and ATE testbenches.
- Design and Development (Verilog RTL) of Telemetry Encoder ASIC/FPGA for Loral's next generation (Omega 3) SCE. This design provides CCSDS frame format and sub-carrier waveform generation with BPSK modulation. Designed NCO module using a micro-controller, to allow for maximum configurability. Designed Configuration Module, where all registers are implemented via a single linear array to avoid multiple instantiations; address decoding via case statement, steers the data. Designed Configuration PROM I/F Module, where data download format includes CRC to ensure data integrity. Wrote Tcl script which extracts Memory Map tables from specification document, and directly modifies Configuration Module Verilog RTL (case statement conditions) to generate register decode tables.
- Helped maintain CVS Repository and Workstation Cygwin for various projects.
Engineering Cover Letter Examples
