Fpga Design Engineer Resume Examples

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FPGA Design Engineers work on the development of new products based on the designs and specifications provided to them by the company's customers. Sample resumes for this position showcase skills like performing traceability between requirements, test cases, and test benches; conducting code linting analyses and subsequent code clean-up; and developing FPGA and system sizing estimates for future designs and research and development efforts. Those interested in applying for this position will need to be able to show a Bachelor of Science degree in the fields of electrical engineering, computer engineering, physics, or another closely related discipline on their resumes.

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1

FPGA Design Engineer

Architected and implemented the on-chip memory interconnect for Convey's MX (large memory) coprocessor, balancing system performance with area utilization.

  • Developed application specific Xilinx Virtex5/6 FPGA builds ("personalities") that accelerated customer applications on Convey's high memory bandwidth coprocessor.
  • Designed components of a Vector Personality Development Kit ("VPDK") that allowed multiple vector applications to be quickly and easily implemented on Convey systems.
  • Created an abstraction layer for the VPDK framework that gave the customer dynamic control over the vector design and created an encapsulated Black Box where the customer could place their highly sensitive IP without having to expose it.
  • Hold a current Government Security Clearance.
Candidate Info
17
years in
workforce
3
years
at this job
BS
Computer Engineering
2

Sr. FPGA Design Engineer

FPGA architecture and design for [company name]'s variety of 40GE, 10GE and 1GE load modules.

  • Worked on wide variety of Xilinx FPGA from Spartan-2 to Virtex-5.
  • Developed and enhanced IP cores for memory controller, Network interface, Microcontroller interface, Checksum Engines, SERDES, etc.
  • Consistently worked on debugging and troubleshooting issues affecting product level.
  • Investigated and resolved customer issues independently.
Candidate Info
12
years in
workforce
4
years
at this job
HS
Electrical Engineering
BA
Bachelor of Arts
3

Asic/fpga Design Engineer

Lead implementation designer of ethernet over SONET and ethernet adaption family of cost reduced solutions in FlashWave series of optical products implemented in Xilinx Virtex 4/5 families.

  • Completed RTL implementation, timing improvement of top level and SONET_FRAMER.
  • Undertook FPGA device evaluation and selection.
  • Completed user timing constraints. Developed and organized scripts, Makefiles for black box, compile point synthesis for process efficiency.
  • Integrated partitions for reuse blocks.Designed chip floorplan in Planahead for timing closure.
  • Interfaced with cross functional teams and successfully resolved issues in pre/post routed designs. Implemented constraint changes/hand edits using FPGA editor to complete the design for critical customer releases.
  • Completed RTL design, integration, and verification of SONET_FRAMER.
  • Completed comprehensive chip synthesis, STA constraints. Improved timing margins.
  • Co-ordinated with cross functional teams and successfully resolved all outstanding SERDES, IP, hardware, software issues.
  • Managed floorplanning including clock tree design, ATPG, Boundary Scan, Power Management and ECO.
Candidate Info
13
years in
workforce
3
years
at this job
BE
Electronics And Telecommunications
4

Sr. FPGA Design Engineer

Architected FPGA hosting a 4K120 video path that includes DipslayPort 1.2 multi-streaming inputs, 4K up and down scalers, frame rate converters, a PCIe streaming frame capture subsystem, and a Vx1 output to the panel.

  • Designed and implemented a clock recovery subsystem for DisplayPort inputs.
  • Managed consulting groups, including Bitec and Omnitek.
  • Worked closely with GPU vendors AMD and nVidia.
Candidate Info
22
years in
workforce
3
years
at this job
Bsee
Msee
5

Senior Hardware / FPGA Design Engineer

Design engineering and technical support for ground support equipment (GSE) used on several space and military programs. Responsibilities include: design and test of equipment used to test and troubleshoot system operations in various development stages. Author of various test procedures as well as several failure modes analysis documents. Expertise in FPGA design and development as well as upgrades to existing FPGA designs.

  • Designated FPGA design lead for Orion Phased Array Antenna (PAA) Program. Lead FPGA designer responsible for VHDL code design in an Actel PROASIC 3 device. FPGA design requirements included: Manchester encoded serial interface to host, Telemetry operations, Parallel in serial operations to system shift registers, Automatic level control, EEPROM interface, and Built in Test. Specific VHDL design responsibilities included: Telemetry operations (ADC reads and temporary storage of data), Parallel in / serial out operations, command interface and telemetry operations. As the lead FPGA designer, responsibilities included knowledge of all FPGA module designs and their functionality and that FPGA functions addressed all customer and internally derived requirements. Insured that FPGA design followed Ball Aerospace FPGA work instruction guidelines, including assurance that all documents were adequately completed, and all formal peer reviews of documents were scheduled and completed. As a lead FPGA designer direct interaction with various mechanical/electrical and system engineers was required. Responsible for critical design review presentation for customer.
  • Critical member of a multi-disciplined engineering team responsible for VHDL code design for a High Accuracy Star Tracker. Targeted device: ACTEL RTAX2000 FPGA. Design responsibilities for command, telemetry and pixel interface between system electronics and star tracker head. VHDL design included power and heater relay control, various time stamp operations and multiple interfaces to embedded block ram for system access and storage.
  • Member of a 2-engineer design team responsible for the design and development of a flash LADAR 3D imaging system. Responsible for board level design, layout and operatonal testing of the electronics hardware. As the responsible engineer for the board design, oversaw a subcontractor designated to produce drawings, layout board and assemble board. Also, directed this subcontractor in the hardware qualification. Completed high-level FPGA design for IRIG, cameralink and SDRAM interfaces and varying degrees of system operations.
  • Lead electronics engineer responsible for system control and power distribution design for 6th generation LADAR system. Responsible engineer for all facets of this design, working with various technical disaplines and divisions within the company to complete the deliverable system.
  • Designed high level mathematical curve fitting algorithims for higher LADAR system range accuracy using VHDL cores and FPGA fabric. Design consisted of multiple stages including multiplication, summing and division that acquired 4 sets of raw LADAR input data and pipelined each section through the curve fit process.
  • Integral part of engineering team tasked to design multiple FPGA-based imaging systems. Responsible for a number of the sub-system designs, detailed FPGA design and hardware board level design. Xilinx Virtex-5, Virtex-4, and Virtex-2 Pro designs incorporated embedded PowerPC, microblaze processors, 1.06 Gbit/sec fibre channel interface, DDR SDRAM video frame buffers, closed loop motor controllers, serial ADC/DAC interfaces, USB 2.0 and DSP functions.
Candidate Info
32
years in
workforce
8
years
at this job
AS
Electronics Technician
BS
Electrical Engineering
MBA
Business Management
6

ASIC / FPGA Design Engineer

  • Architected and designed major sections of large ASICs including Verilog source, synthesis, testing, and integration. Coordinated work of several engineers.
  • Verified operation of very complex Sonet/SDH and 10GE network communications ASICs using mixed VHDL/Specman-e co-simulation. This new flow increased ability to find problems and speed up testing.
  • Developed FPGAs to test ASICs. This was needed for hardware debugging and firmware development.
Candidate Info
14
years in
workforce
3
years
at this job
BS
Electrical Engineering
7

FPGA Design Engineer

Developed NSA Suite B Crypto Engine Embedded with Diamond 106micro in Xilinx Virtex 6

  • Developed HDL that utilized Xilinx PCIe core & Intelliprop Sata Bridge core for Cyber collection in Virtex 5
  • Developed HDL that used in Next Generation sATCOM Terminal in Xilinx Virtex 5
  • Re-Targeted a UDP based core from Xilinx Virtex 6 to Xilinx Virtex 7
  • Developed & Integrated Imaging algorithm targeted for Xilinx Zynq-7000
  • Developed Control System targeted for Xilinx Virtex 7 using ADC & DAC
Candidate Info
20
years in
workforce
5
years
at this job
Electrical Engineering
8

FPGA Design Engineer

Ownership of digital hardware domain responsibilities, integration of DSP/networking IPs for high-speed low-latency communication

  • Responsible for developing and testing lock-in amplifiers, PLLs, IIR filters in Verilog for implementing controller architecture.
  • Developing firmware to communicate between ARM processor and programmable logic on the Zynq All-programmable SOC.
  • Wrote socket programming in Java and C to enable TCPI/IP communication from PC client to FPGA server
  • Performed and validated BERT tests with near end PCS/PMA loopback for testing transceivers on the ZC-706.
Candidate Info
4
years in
workforce
1
year
at this job
BE
Electronics And Communication Engineering
MS
Electrical And Computer Engineering
9

FPGA Design Engineer

  • Responsible for enhancement and maintenance of FPGA and CPLD firmware for 4 different variants of Supervisory Control and High-Speed Data Acquisition devices for a client in the power quality monitoring industry
  • Behavioral and VHDL RTL description of digital circuits and functional simulation through test-benches
  • Provided solutions through FPGA to various PCB related issues
  • Involved in synthesis, place and route and ensuring timing closure for the designs
  • Performed functional verification and design modifications in the gain switching part of a signal processing module implemented on Xilinx Spartan-3 FPGA for the samples acquired from a bipolar ADC. The processing included 2’s complement – binary – 32 bit floating point conversion, gain switching, gain multiplication and offset correction for the acquired ADC samples.
  • Enhancements to the module which performs continuous calibration on the FPGA’s internal clock to meet data sampling rate accuracy of 10 us. External time sources like GPS, RTC and IRIG-B used for clock drift management.
Candidate Info
3
years in
workforce
3
years
at this job
BE
Telecommunication Engineering
MA
Engineering
10

Asic/fpga Design Engineer

GS Communications Systems _ Active security clearance. Participated in the design and development of tactical software radios for various military platforms. Also, designed and simulated FPGAs for cryptographic and Information Assurance subsystems.

  • Developed RTL coding in VHDL, conducted verification with Modelsim, coded test -benches and procedure packages, synthesis with Synplify Pro and place & route with Quartus II (Stratix II, Cyclone III) and Xilinx ISE (Virtex) in a collaborative enterprise work environment. Implemented FIR, IIR and CIC filters and DSP communication algorithms in FPGAs developed with Catapult C and Matlab and familiar with System Verilog.
  • Developed Test plans and testcases in the verification of top as well as lower level blocks that cross referenced requirements in a traceability matrix. Verified Ethernet packets and other communication protocols as well as security algorithms.
  • Conducted Requirements capture and peer review, and developed technical documentation, design verification, and test specification.
Candidate Info
14
years in
workforce
3
years
at this job
Electrical Engineering
Electrical Engineering

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