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Asic Verification Engineer Resume Samples
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0-5 years of experience
Involved in pre-silicon validation/verification of modules Payload Manager (PM_RX and PM_TX) in the 10G Ethernet chipset using Verilog and VERA.
- Developed a testplan and setup the testbench and the environment
- Filed bug reports, verified rtl fixes, analyzed test results and performed coverage analysis.
- Wrote test cases using VERA to test the functionality of the modules.
- Debugged rtl using simulators like NC-Verilog, Simvision, and Synopsys VCS.
- Involved in writing and modifying Perl scripts.
0-5 years of experience
Verified and debugged SoC portion of ARM7TDMI based design, for Bluetooth applications. Wrote test cases in C, C++, Verilog HDL and Vera to test at both chip and module level. Ran simulations to verify functionality at both rtl and gate level.
- Ran gate level simulations with post layout timing information to verify timing.
- Developed monitors in Verilog HDL to track uniformity of flash access lengths and also relationships between clocks in the background.
- Wrote test plan and test cases focused on thoroughly testing the DMA-UART-Buffer Access Controller working in a Vera environment. Implemented Vera test bench for random testing.
- Wrote detailed test plan and test cases to test System Timer. Generated and simulated with ATPG scan vectors. Generated code coverage information using Coverscan.
0-5 years of experience
- Developed, verified, and tested next-generation digital TV frame-rate compensation ASICs for LCD panels
- Wrote and executed verification test plans (block and chip level) for multiple sub-blocks within ASICs
- Designed and implemented RTL code changes to existing sub-blocks for ASIC performance enhancements
- Critical member of bring-up team for verifying and characterizing first-generation ASIC through entire process from initial voltage / interface testing to final customer (on-site) manufacturing and firmware support
- Provided verification environment support and training both on-site and remotely across multiple sites for different ASIC teams and projects (Pennsylvania; California; Shanghai, China)
0-5 years of experience
Primary Responsibilities include testbench development, testcases generation, regressions run and analysis, functional and code coverage run and analysis, running gate level simulations and regressions, running gate level simulations with SDF, developing and optimizing scripts for pre and post processing.
- Worked on 802.11 PHY Baseband block on 3 projects where we developed and enhanced the testbench environment and created testcases for different sub-blocks and different scenarios.
- Worked on the digital block of 2 RFIC chip projects where I worked on testbench and testcase development. Worked on SPI Master and Slave Block for RFIC projects.
- Assisted in development of constrained random verification environment with functional and code coverage and development of scripts pertaining to simulations and regressions.
- Worked on regressions and simulations with RTL, Gate and Gate with SDF.
0-5 years of experience
Wrote system and unit test cases to verify functionality and performance of Exascale switcher/router SOC capable of L2 & L3 packet processing at line rates of 50x1G & 5x10G and over subscription rates of 100x1G & 20x10G. Traffic includes IPv4, IPv6 encapped in Ethernet(802.3) and EV2. Developed test suits, parsed and extracted results from log files.
- Executed test cases to verify Xilinx FPGA that does access based filtering of packets destined for RPM cpus.
- Executed over 80 system tests to verify control, mirroring functions and performance.
- Executed over 400 unit tests to verify IP fragmentation, Mirroring, ICMP, Logging, Sflow of data and control traffic in Ingress and Egress pipes.
- Executed over 170 module level mirroring tests(functional and performance ). Verified BW allocation of all ingress and egress pipes.
0-5 years of experience
Worked as a Verification Engineer for VCS tool development.
- Validated IPXACT 1.5 and DVE VCS tool features for beta release and filed number of bugs.
- Responsible for regression scripting and failure Analysis.
- Served as “Joint Secretary” of Basaveshwar Engineering College IEEE Student branch. Jan’09-Jan’10
- Awarded as best outgoing student of Instrumentation Technology, Jun’2011
0-5 years of experience
- Created verification plans and built testbench and testcases for synthesizable PowerPC microprocessor
- Developed memory model with targeted random instruction sequences and data
- Performed formal assertion proof verification using 0-in tools (now Questa Formal Verification)
0-5 years of experience
- Implemented C models for the functional verification of a multimode (GSM, GPRS, EDGE and WCDMA) System on Chip (SoC) for mobile devices.
- Integrated and verified the physical layer blocks within the base-band chip.
- Implemented SystemC PLI calls to integrate fixed-point reference model within Verilog test environment.
- Independently developed and maintained the automated system level test environment in UNIX (using PERL and Shell scripts).
- Co-authored conformance test plan, verification strategy and enumerated all the test cases to be developed.
- As a prime of system level verification for the wireless modem, documented extensive Test Release Reports which were delivered to potential customers.
- Responsibilities included: execute top-level regression test cases in automated mode, investigate and debug defects, elevate issues to designers and maintain the verification database.
0-5 years of experience
Implemented and verified NOA (Node Observed Architecture) using System Verilog.
- Designed, designing for debug (DFD) features of hierarchical muxes and verification by writing RTL code generation.
- Development of Verification plan and Test plans.
- Functional and Code coverage coding.
- System Verilog environment coding.
- System Verilog and Universal Verification Methodology (UVM).
- Performed Assertion based verification.
- Wrote and implemented verification environment architectures.
0-5 years of experience
3 years of experience in: ASIC Design cycle, methodology and Verification
- Experience in verification of ARM based SoC(System on Chip) at RTL level and gate level
- Experience in DFT(Design for Testability) testing of GPS(Global Positioning System) block in ARM based SoC
- Hands on experience in low power verification using CPF(common power factor)
- Sound knowledge of PCI Express bus
- Extensive knowledge of functional verification, developing test bench using System Verilog/OVM and strategy for testing, reporting and analyzing test results
- Authored range of documents including requirement specifications, Verification plan definition, Hardware design documents, testplan and user manuals.
- Hands on experience Perl and Shell scripting, VMM methodology
- Development of OVM compliant OVC(Open Verification Component) of Single wire protocol (for SWP verification) & Slimbus bus protocol
0-5 years of experience
Designing verification components (monitors, metacheckers, and protocol checkers) and constrained-random tests for a multi-million gate PCIe interface ASIC using Verilog, Specman/e, and perl.
- Designed base packet data structure and subclasses used by all verification components.
- Designed bus interface monitor.
- Designed bus interface block metachecker (scoreboard).
6-10 years of experience
- Using C, assembly language and Linux/UNIX skills, I developed tests that verified the reliability of the homegrown threaded processor that powered the [company name] 4G LTE router. Strong performance led promotion.
- Responsible for performance evaluation, optimization, and tuning of the network processor’s low level software.
- Received multiple awards for top performance (including recognition in the top 7% of employees).
0-5 years of experience
Verification lead for full chip and USB/UWB MAC
- Developed Cycle accurate Architectural RTL Model for MAC
- Design and Developed Methodology for MAC and Full chip verification
- Developed scripts for automating tests, regressions and analyzing results
- Developed Wireless USB Host Model( eRM complaint eVC)
- Developed Driver Model to Program DMA and other Hardware
- Developed scoreboards and protocol checkers to check packet data
- Developed Co-Verification Environment(HW/SW) using Seamless for ARM 968ES
- Mentored the team in writing test bench components and test cases
0-5 years of experience
- Performed detail state machine analysis and debugging.
- Focused on Gigabit fiber optics Ethernet interface and operation.
- Familiar with fiber optic blocks such as Serdes20-bit/10-bit, 8B/10B Encode-Decode.
- Designed industry first 10/100 LAN+56K Win modem TypeIIIA MiniPCI network card.
- Designed a 16-bit PCMCIA 10/100 Ethernet PC card.
- Designed schematics using Viewlogic Powerview, Allegro, and Visula tool environment.
- Experience in high speed PCB design, board layout / route to enhance EMI scan.
- Understand PCMCIA / CARDBUS / MiniPCI bus interface structure.
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Asic Verification Engineer
Last edited by: Gabriela Barcenas, CPRW, Content Writer II -
Gabriela Barcenas
CPRW, Content Writer IIGabriela is a Certified Professional Resume Writer (CPRW) and career adviser. With 10 years of digital media experience and five years of resume writing expertise, her publication history includes fashion, education, travel, social justice, equitable design and career advice.
