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Asic Engineer Resume Samples
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0-5 years of experience
Developed chip-level and block-level verification environments for 2nd generation Gigabit routing and cross connect ASIC using Verisity Specman.
- Developed verification environments for various “Gigabit routing and cross connect ASIC” modules such as Framer, Media Access Control, Scrambler, SERDES, and Frame Aligner. Also wrote verification plan and developed directed and random tests. All the tests were self checking. The checking was done using scoreboard and reference models.
- Developed functional verification environment for DS3 mapper ASIC using Verisity Specman. Wrote verification plan and developed directed and random tests. All the tests were self checking. The checking was done using scoreboard and reference models.
- Extracted and analyzed coverage data using Surecov tool.
- Developed regression and post processing automation scripts using Perl.
- Developed chip-level verification environment and performed verification for 1st generation Gigabit routing and cross connect ASIC using Verisity Specman.
0-5 years of experience
Worked and made solid contributions to a SSD SoC project. Specific duties included: RTL based hardware design in Verilog, large scale logic synthesis, low power implementation and verification, static timing analysis, and formal verification using Synopsys and Cadence EDA tools. Came up to speed very quickly on using the new EDA tools.
- Extensively used Perl and TCL programming languages to drive the tools as well as UPF and CPF development for power island implementation.
- Collaborated with the verification team to execute directed test simulations using System Verilog and VMM for the SSD SoC projects.
- Collaborated with the verification team to prepare MVSIM verification plan, compiled the flow to integrate UPF with MVSIM and ran MVSIM to dynamically verify power-managed multi-voltage SoC designs.
0-5 years of experience
Key contributor to the development of three ASIC chips, two of which went into production in 65nm TSMC LP process, and the third, in 40nm TSMC process, is awaiting customer approval for test parts.
- Main designer of a CPU subsystem which consisted of integrating a Synopsys ARC601 CPU, a HDMI 1.4 interface IP, SRAM, an I2C interface, an AES decryption module, a SPI controller, and a video upscaler on an AHB bus. Wrote interfaces using Verilog RTL so that all modules were able to seamlessly operate together on the AHB bus to form a fully functional system. Wrote Verilog testbenches to verify the entire subsystem which has been fully functional and extensively used on two production ASICs.
- Implemented a major 2 million-gate video noise reduction module in Verilog RTL. Individual submodules were coded in Verilog RTL; subsystems were verified against C models; and each block was synthesized using Synopsys Design Compiler.
- Implemented a gamma correction module. The module was synthesized and integrated into the video data path of three ASICs.
- Performed static timing analysis on an 8 million-gate, 8 clock domain, ASIC using Synopsys PrimeTime.
- Performed equivalence checking on various submodules using Synopsys Formality.
- Performed ECOs on post layout netlists to do metal layer bug fixes.
0-5 years of experience
Performed design changes and developed test-benches on the Buffer Manager, Disk Formatter, Servo, and Signal Pulse Generator blocks on a customer’s ASIC
- Participated in the design of a full chip test bench suite to validate the operation of the customer’s ASIC
- Developed behavioral code and test benches for the design and verification of the Serial ATA module
- Implemented RCS for revision control to checkpoint design files
6-10 years of experience
Responsible for the specification, design, and verification of digital logic implemented in ASICs and/or FPGAs for use in wireless communication systems. Participated in the evaluation and recommendation of design tools for use in the ASIC design and verification process. Designs were done in VHDL, Verilog, and SystemVerilog.
- Participated in the specification, design, and verification of chips used in IEEE 802.11 wireless systems. Design assignments included clock recovery logic, content-addressable lookup, binary search engine, ethernet remote monitoring (RMON MIB, RFC 2819), JTAG (IEEE 1149.1) boundary scan, and interfaces to various external devices. The chips went into production with no re-spins and have been used in numerous wireless products.
- Collaborated with design groups in remote locations, which required accurate communication and coordination of efforts. Achieved seamless integration between modules designed in different locations.
- Assisted in the development of standard documentation templates, design and verification procedures, and various tool usage tutorials providing a documented design process in compliance with ISO 9000. Several of the items developed were considered “best practices” within Cisco.
- Maintained the tools, licenses, and libraries used by the ASIC group. Adapted and maintained a wrapper system, allowing team members access to all ASIC tools without exceeding the limits of various system variables. This also enabled all users to utilize the same, latest versions of the tools, thereby reducing errors caused by using conflicting tool versions.
- Created a method to automatically update the list of valid license servers for each tool, thus preventing tool errors due to incorrect LICENSE paths.
10+ years of experience
Carried out design, RTL coding, simulation, synthesis, timing check, system integration, and test case functions, ensuring compliance with unified test plan, as part of basic design flow responsibilities.
- Communicated closely with senior engineers for technical design and applications for new designs.
- Conduct whole chip synthesis, debugging and test vector generation for production.
- Performed all design flow activities for VersiCore project, targeting reusability in general bus architecture. Project involved RISC CPU core, general bus structure, RTL coding, and front end design work.
0-5 years of experience
Micro-architecture design, RTL coding for I2C and Vedio blocks for Trimedia graphic multimedia processor chips.
- SOC integration for DFT logic including scan chain, MBIST and JTAG logic.
- Performed Verplex equivalence check, ATPG and static timing analysis.
- Supported tape out activity and gate level simulation with SDF back annotation. Silicon brings up and debug in ATE and lab.
0-5 years of experience
Responsible for the architecture and design for MAC_PHY interface of 802.15a Phy and MBOA MAC.
- Architected and designed control logic for the Transmit and Receive chains of the base band design running at 533 Mhz.
- Integrated the Receive and Transmit chains of the base band.
- Architected and designed various blocks of the base band. These included but were not limited to Interleaver, deinterleaver, modulator, demodulator, puncterer, depuncturer, channel estimation, phase equalization, time drift, encoder, all running at 533 Mhz.
- Worked closely with several comm. System Engineers to perform cycle accurate validation of various Physical layer RTL designs with fixed point C models.
- Responsible for designing the base band, Radio interface.
0-5 years of experience
Facilitated customer completion of all requirements of [company name] methodology prior to release to manufacturing of customer designs. Handled customer and [company name] Team inquiries.
- Provided customer with DRC/LVS/RC extraction and simulation, as well as IP testing and mixed signal testcase development, supporting customer integration and improving time to market of parts.
- Taught customers to use [company name] IO Scan Insertion tools, Insert [company name] or IEEE 1149.1 boundary scan, IO padring into the design top level, while facilitating pin sharing, improving customer satisfaction.
- Taught customers to use Netlist Processing tools, convert flip flops to scan latches ([company name] LSSD), and perform [company name] scan chain balancing.
- Clock Tree Creation and Insertion tools, creation of functional clocks.
- Static Timing, Debug timing assertions and help them close, timing.
6-10 years of experience
Member of the ASIC team that designed RAID controllers, SCSI, and SATA host bus adapters. Responsibilities included ASIC design conception and enhancements to increase performance and reduce cost of the PCB’s.
- Developed Verilog bus functional compliance models for use with an internal proprietary bus interface. The models were adapted for use throughout the company.
- Designed multiple generations of RAID DMA engines. The result was an increase in performance of the RAID controllers.
- Designed memory (EDO DRAM, SDRAM and FLASH) controllers.
- Created VHDL ASIC simulation model for use with system testing.
- Generated test and functional vectors for ASIC’s. This included test software written in C to verify operation of embedded processors and SCSI cores.
- Performed PCI bus compliance testing.
- Designed JTAG controllers and I/O interface logic.
0-5 years of experience
Responsible for Specification, design, HDL implementation, verification, simulation and documentation of various blocks of a multi-million gate DSP and contributed in four tape-outs and two SOC products as a joint project with Freescale.
- Memory Design for test-ability (MBIST) using Virage Logic STAR Memory System.
- JTAG and NEXUS 5001 Debug support using IEEE 1149.1 standard
- Test-bench and C/Assembly test case development.
- Worked closely with FPGA group for pre-silicon verification
- Customer/documentation support
0-5 years of experience
- Architected and designed the Write Manager with Weighted Round-Robin Arbitration Scheme and Rate Limiter to achieve host 500K IOPs write throughput and to balance the multiple sources write data transfer bandwidth.
- Architected and designed the READ Manager to handle the queued multiple destinations’ read commands. Each destination’s read command runs independently and is pipelined to achieve host 1M IOPs read throughput.
- Implemented the atomic command handling mechanism in Read/Write data path.
- Involved in auto command handling architecture and design.
- Helped on debugging the Command Processor/Read-Modify-Write modules, Command Manager sub system and chip level verification and FPGA validation.
0-5 years of experience
- Implemented a serial data packet processor to collect incoming packets, validate them, parse the data, and then generate internal commands to the rest of the system. (It also would collect responses from the internal devices, build up outbound packets and send them out along the bus.) The completed design consisted of multiple clock domains; filled a 600,000 gate Vertex 4 FPGA.
- Coded a serial packet test bench to stimulate not only the data packet processor design, but all other chips within the system (third party chips were modeled). The system created randomized data packets with different data flows, and supported directed tests. Implemented in both VHDL and Verilog.
- Designed a STM-16 packet processor by following the G.707 specification to break the data streams down into their fundamental L1 connections; reorganize the streams and rebuild the output flows on the fly. Data could be injected and any L1 stream could be stripped out/changed on the fly. Implementation was done in a Xilinx Vertex-II 6000 FPGA.
- Generated a Verilog test bench to randomly generate STM-16 data streams of random configurations into the STM-16 packet processor. The data output data streams were then automatically validated against the input data to verify functionality.
0-5 years of experience
Designed and verified VLSI (ASIC & FPGA) of image/video processing algorithms for Digital/Analog TV system.
- Reduced PDP false contour algorithm design and drove controller design.
- Designed Analog TV decoder.
- Designed an Architecture of Motion Estimation Algorithm for Digital Display (Memory Scheduling and Complexity Adjustment).
- Designed the Digital Natural Image engine (DNIe TM) IC II (Adaptive 3D Noise Reduction De-blocking, De-ringing, Memory Management).
- Designed the DNIeTM IC (Noise Reduction block with VHDL).
- Designed the Driver IC for PDP TV (PDP XY control driver and false contour reducing block with VHDL).
- Designed digital decoder IC for analog TV (Digital 3D Comb filter with Verilog HDL: KS0129 TV decoder).
0-5 years of experience
- Involved in Design and Verification of Ethernet Management Interface (MDIO) Block. Contributed towards test cases and test bench development as well as synthesis
- Implementation and validation of low power scan DFT methodologies (For CPU) – Segmented Scan
- Involved in Scan Synthesis and Scan Insertion for various modules
10+ years of experience
Developing Verilog codes for Pixel Rendering for PenTile layout panels (RGBG, RGBW).
- FPGA Evaluation with Altera, Xilinx.
- Designing the Front-End RTL code of PenTile IP for making ASICs
- Developed many peripherals such as LVDS I/F, SDRAM I/F, I2C I/F etc.
0-5 years of experience
- Building verification environment and verification of MHL (Mobile High definition Link)
- Written scripts to automate the process of verification using perl, cshell.
- Worked in a team of 5 and involved in all stages of project life cycle including requirements
0-5 years of experience
Identified system needs for new analog asics across the business.
- Created Specifications for asics.
- Created test plans to qualify asics
- Defined and Patented unique digital interface for analog asic driver for printheads.
- Managed projects with major ASIC suppliers in the industry Motorola, TI, and ST.
- Drove implementation across internal divisions and ODMs for analog asics.
0-5 years of experience
- Hspice simulation on I/O buffers, full chip floor planning, partition, and aspect ratio assignment.
- Writing Drcula and modifying LVS and DRC tech file, I/O buffers layout and IBIS model setup.
- Performing advance graphic and multimedia chip design related tasks which including schematic entry and netlisting, layout planning and detailed custom layout, block and top level editing, full chip Dracula LVS, LPE, DRC verification and final chip tape-out.
6-10 years of experience
Design analog & digital circuits using Cadence layout and schematic Virtuoso
- Simulating mix-signal designs using Cadence Virtuoso AMS and Cadence Virtuoso Multi-mode
- Design and Analyze clock and data network to increase print speeds
- Developed LabVIEW code to control test equipment, analyze data, and assist in mass data collection of functional & characterization circuits
- Create Verilog/Veriloga code to describe and test circuits at modular level and system level
- Functional testing on various circuits of the heater chip
- Initial LabVIEW code design for automation
- Work with lead engineer to correlate data with partnering company
0-5 years of experience
- Integrate CEVA-SATA AHCI Host Controller IPs with RENESAS’s SOC3 SATA system for the ASIC group to design next generation SOC chips.
- Built and simulated the host controller, interface components, and PIPE wrapper by using Qsys Integration Tool under Quartus II.
- Implemented and verified on an Altera’s Cyclone V FPGA board with SerialLite II protocol.
0-5 years of experience
- specified full architecture/design/testing of pci to ethernet fpga for production
- led Specman-based verification effort on ethernet cross-bar switch ASIC (pre/postSi)
- worked remotely for three months from Guadalajara, Mexico
0-5 years of experience
Designed USB module for Wide Band Home RF ASIC. Used a InSilicon USB 1.1 core, designed interface logic using Verilog-XL and Synopsys. Ran module level simulations using SignalScan and InSilicon USB Host bus model. Ran chip level simulations using SignalScan, USB Host Bus model, and ARM assembly.
- Designed emulation board for Wide Band Home RF ASIC using Altera APEX (20K) FPGA, ARM processor, SRAM, Sync SRAMs, high speed DACs, and A/Ds. Board used for ASIC system verification. Designed interface logic for A/D and DACs (in FPGA) using Verilog.
- Designed interface module board/logic using Altera 10K30 FPGA, Verilog, and MaxPlus II.
- Defined and designed the USB 1.0 module for the Proxim 1.6 Mb Home RF ASIC. Used an InSilicon USB 1.0 core, designed interface logic using Verilog-XL and Synopsys. Ran simulations using Cadence SimWaves and InSilicon USB Host model.
- Designed an ISA PnP module for the Proxim 1.6 Mb Home RF ASIC using Verilog-XL and Synopsys.
- Designed two test/reference boards for ASIC verification and initial product development for both the 1.6 Mb Home RF ASIC and the Wide Band Home RF ASIC.
- Designed two emulation boards for 1.6 Mb Home RF ASIC emulation environment, used Altera Flex 10K100, RAM, ROM, radio modules, PC interfaces (ISA, PCMCIA, and USB).
- Designed the digital sections of the Proxim Symphony Home RF Products (based on 1.6 Mb Home RF ASIC): USB, PCMCIA, Ethernet Bridge, and Micro ISA products.
- Designed digital section of Symphony ISA PnP Wireless LAN board using Proxim 82374 ASIC, National PnP ASIC, and discrete logic. Worked on the product definition of wireless PCI based product. Designed digital circuitry for the Proxim Symphony Cordless Modem. Used embedded 80186 controller, DSP, FLASH, SRAM, and FPGA. Developed Lattice FPGA module using Verilog-XL and Synopsys.
0-5 years of experience
Programmable General Purpose Counter: The project was to develop a synthesizable PGPC core in Verilog.
- Design development RTL of PGPC core
- Static and Dynamic Timing Analysis
- Development of test bench for verification in Verilog
0-5 years of experience
Programmable General Purpose Counter: The project was to develop a synthesizable PGPC core in Verilog.
- Design development RTL of PGPC core
- Static and Dynamic Timing Analysis
- Development of test bench for verification in Verilog
0-5 years of experience
Developed multi-million gate FDD modem prototype
- Designed modem modules for 3G wireless
- Simulated, coded, and tested VHDL and CoWare
- Coverage analysis using Verification Navigator
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Last edited by: Gabriela Barcenas, CPRW, Content Writer II -
Gabriela Barcenas
CPRW, Content Writer IIGabriela is a Certified Professional Resume Writer (CPRW) and career adviser. With 10 years of digital media experience and five years of resume writing expertise, her publication history includes fashion, education, travel, social justice, equitable design and career advice.
