ASIC Design Engineer
Responsible for developing golden model, logic design, test bench, extracting layout parameters, pre/post layout verifications, timing analysis(Hspice) and backend support of 0.6u, double metal, 64-bit cascadable Single nibble error correction, Double nibble error detection (S4EC-D4ED) custom chip using Fujiwara block codes. Developed power bus scheme, clock trees and drivers. A thorough critical path, switching and electro-migration analyses were done using 256 pin BGA parameters and Hspice. Device worked to all specifications first time.
- Redesigned and verified 0.6u, 64-bit cascadable Single error correction, Double error detection (SEC_DED) chip using modified Hamming block codes.
- Redesigned 15 double density and octal family products to faster, smaller geometry arrays and new processes. Devices included FCT, LVCMOS, High, Balanced, BD-Lite and CMOS drive types.
- Designed pre-scalar, post-scalar dividers and control logic for PLL devices.