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Ic Design Engineer Resume Samples
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Candidate Info
3
years in workforce
3
years at this job
BA
Materials Physics
MA
Applied Physics
IC Design Engineer and Project Leader
- Built up prototype of integrated circuit with FPGA and completed function verification.
- Designed product specification as well as development plan.
- Designed digital circuits with Verilog and VHDL language.
- Maintained open and effective communications with project teams to increase productivities.
- Completed 4 projects (total 6 ICs) and applied a patent on remote control algorithm (TDMA).
Candidate Info
20
years in workforce
9
months at this job
HS
Physics
BS
Electrical Engineering
MS
Electronic Systems Design
Senior Staff ASIC Design Engineer
Successfully taped out Hermosa (0.18um) project from synthesis, scan insertion, LEC, STA timing closures and scan simulations and debug.
- Worked on IO interfaces timing closures on PecosB and Nevis projects. Both are 90nm technology and about 25-million gate designs.
- Worked on Nevis top level synthesis and generated top level SDC for timing driven layout.
- Worked on test cases to explore the features of Fish Tail timing exceptions tool and Prolific timing and power optimization tool.
Candidate Info
2
years in workforce
2
years at this job
PhD
Doctor of Philosophy
Msc
Bsc
Mixed Signal IC Design Engineer
- Implemented Prescalar and ESD structures for dual synthesizer family of chips in the range of 1.2GHz-6GHz and 500MHz-2.5GHz in 0.5•m SiGe BiCMOS technology (SKY72300, SK72310, SKY72312)
- Phase noise was -85dBc/Hz at 10kHz offset and spurious was below -60dBc
- Prescalar blocks designed using CML logic
- Efficient ESD structures handled up to 2.5kV
- Acting project prime near tape out and managed 5 designers and 2 layout engineers
Candidate Info
9
years in workforce
7
years at this job
BE
Electronics
Electronics
Project Management
Analog IC Design Engineer
- Designed a 10Gb/s serial data transmitter and a 16:1 (625Mb/s to 10Gb/s) parallel to serial data MUX for SerDes chip in 130nm CMOS. Work included: schematic entry, simulation, custom layout and initial lab verification
- Simulation, schematic entry and custom layout work for DC bias blocks, bandgap voltage references, high speed logic cells (CML), 10Gb/s low noise receiver, PFD, CDR
- Chip level ESD protection design and integration
- Top level floorplanning and schematic/layout integration and physical verification for tapeout
- ESD test-chip design for 90nm, 130nm, 180nm CMOS/BiCMOS processes
- Troubleshooting of ESD and latch-up issues; failure analysis
Candidate Info
4
years in workforce
4
years at this job
PhD
Electrical And Computer Engineering
Electrical And Computer Engineering
Electrical And Computer Engineering
ASIC Design Engineer
- ASIC design team member for 4 projects (GPS, ADSL, WLAN, GSM)
- Design technologies include digital/analog/mixed-signal
- Gate array, standard cell, and full custom architectures
- Comprehensive functional verification cycle of all IC designs
- DSP Programming for a G.Lite ADSL System Evaluator
- Designed and developed fax interface for GRS-3 (GSM TelephoneInterface)
- System-level behaviour simulations for Mixed Signal chips
- Designed PCB for 10 watt Ballast (low consumption lamp)
- Verilog RTL coding for several project
Candidate Info
29
years in workforce
2
years at this job
BS
Electrical Engineering
Senior ASIC Design Engineer
- Owned all aspects of the build of various Memory Controller Blocks
- RC for synthesis
- Innovus for Place & Route
- Tempus for timing closure
- Voltus for power closure
- Architected and built ARM Cortex sub-systems in 28nm and 16nm ensuring performance, size and power
- Defined power integrity verification flow using Cadence Voltus
- Helped implement EDA design flow using Cadence EDI and later Innovus tools
- Architected, coded (Verilog) and verified (UVM) silicon characterization blocks used on 28nm test chip and coded firmware utilization.
- Member of SSD security team
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