Senior IC Physical Design Engineer
Top level floor planning, layout, and full chip verification of 10Gb/s (OC192) transceivers designed to address future systems of 40Gb/s (OC-768), using TSMC .13um technology. Circuits included: VCOs, VCOBuffers, Demuxes, Voltage Regulators, DACs, Loopfilters, Ring Oscillators, Bias Blocks, ESD Structures, standard cell libraries, and other various high speed digital blocks.
- Handled and implemented standard design kit elements. Elements included: interdigitated metal capacitors, inductors, varactors and transmission lines. Mentor Graphics rule deck development using Skill code language.
- Proficient Cadence and Mentor Graphics tool experience. Familiar with IBM, Lucent and TSMC foundry procedures; .5, .35, .18, .15, .13, .09um (Lucent/TSMC), 7SF, 7HP, 6HP, .18, .13um RF CMOS and LVOD.
- Experienced in matching, electron migration, symmetry, power busing, balancing of critical signals and IR drop.