Analog Design Engineer Resume Samples

Analog Design Engineer

• Initiated and led 28nm chip project, assigned roles and responsibilities, designed workflow, trained team members on different tools as a result saving 7months of design time for the succeeding project.
• Communicated with cross-functional teams to share resources resulting in a cost saving of ~$70k.
• Convinced upper management to sponsor the training on design tools for the team that resulted in increased efficiency of more than 2 months in the schedule.
• Designed a pipelined ADC architecture for 28nm technology that reduces the chip area by 5% with potential savings of $6mil over the next 5 years.
• Designed VGA circuit for 1Gig Ethernet chip that cut the chip cost by $200K by reducing chip area by 20mm^2.
• Created workaround for powering up issue of a chip before sending samples to customers, winning the customer contract worth $600K as a result.

Senior Analog Design Engineer

Part of R&D group to define and design a most advanced laser sensor implementing relativity theorem to measure rotational.

• Debugged and redesigned part of emulator's circuit to test Gyroscopes.
• Created and modified power supply schematics. Debugged and troubleshoot firmware of Emulator to simulate optical sensors. Designed and developed analog circuits to support optical applications such as: Rotation Sensors and Gyroscopes.
• Responsible for component quality analysis to meeting Military Requirements and Electronic Critical Design Review (ECDR).
• Experienced with the lasted Fiber Optic Gyroscope (FOG) technology.

Analog Design Engineer - Synthesizer and Transmitter Groups

Design of RF and PLL circuits for polar modulation based RFICs for UMTS cell phones

• Successfully designed and validated a High dynamic range, single stage Variable Gain Amplifier for a UMTS Tx.
• Implemented an LC VCO Coarse tune calibration circuit in a .25u SiGe process
• Designed a low power 4GHz WCDMA prescaler for a UMTS transmitter In a .25u SiGe process
• Set up and administered a Synchronicity DesignSync based version control system for the Cadence design database
• Helped develop a Mixed signal simulation flow using SpectreVerilog and AMS/Spectre/UltraSim for simulating PLL calibration circuits

Analog Design Engineer

Acquired $50,000 of IR&D money to design and develop Dual Series Boost Regulator Power Management and Distribution System for laboratory test configuration of a Solar Array system. Procured hardware, created assembly instructions, assembled prototype and tested IR&D Dual Series Boost Regulator Power System. Performed worst case and root cause analysis on the control system to the component level.

• Responsible for procurement, assembly and creation of Engineering Product Development documents for the Orion Portable Equipment Panel (PEP). Utilized space hardened avionic hardware to create engineering product parts list. Utilized Flyback Current-Fed Push-Pull topology with a Weinberg inductor and Voltage Mode Control circuitry.
• Designed, acquired hardware, created product development instructions and assembled complex product prototype of the J-2X Engine Controller (EC) Backplane including testing and creation of Printed Wiring Board Design Instructions. The EC Backplane routes the 1553 Data Transmitter bus, Valve Actuator Control, Thermocouples, Pressure and Accelerometer data. Supported the J-2X Engine Controller through production and test.
• Performed worst case circuit analysis and created Engineering Product Development documents for the J-2X Spark Exciter. The Spark Exciter is part of the J-2X rocket engine ignition system that utilized an inductor and capacitor system to ignite the rocket engine fuel.
• Performed worst case circuit analysis and created Engineering Product Development documents for the Speed Sensor Signal Conditioner. The Speed Sensor Signal Conditioner provides speed and flow turbo pump data during rocket engine run time.
• Responsible for design and development of the Multiple Kill Vehicle (MKV) Test System Software GUI. The MKV Test Systems GUI interfaced with Reflective memory and an Ethernet bus while utilizing User Datagram Protocol, Multithreading, Inheritance and Polymorphisms. Utilized MS Visual C++ for design and integration.
• Responsible for the maintenance and delivery of Kinetic Weapon Control Systems to customers in Maryland's Johns Hopkins University ( Applied Physics Lab), White Sands Missile Range (New Mexico), Boeing (Anaheim, California) and Raytheon (Tucson, Arizona). The Control Console utilized RS232 Bus, RS422 Bus and VXI Control Systems with a proprietary power control system.
• Design engineer responsible for the design and procurement of the RS84 Data Acquisition System which included the Resistive Temperature detector Conditioner circuitry, the Pressure Signal Conditioner circuitry, and the Variable Reluctance Sensor Interface. The data acquisition system utilized the Compact PCI bus (cPCI).
• Responsible for assembly instructions, hardware procurement, operational analysis, environmental performance and acceptance testing of the Direct Current to Direct Current Converter (DDCU). The converter is an Orbital Replacement Unit for the [company name] that supplied 6 kilowatts of direct power.
• Performed thermal and vacuum testing of Orbital Replacement Units (ORUs) developed to power the [company name]. Thermal and vacuum testing consisted of utilizing environmental chambers and test consoles developed to perform Low Earth Orbit (LEO) simulations.

RF / Analog Design Engineer

Responsibilities centered on redesign and debugging of electronic modules inside Datron's Tactical Radio products.

• Redesigned and debugged synthesizer for VHF tactical radio.
• Designed of RF power amplifier for future VHF tactical product.
• Debugging of HF antenna tuner. This included programming an Intel 8051 micro controller in Assembly language.

Analog Design Engineer

• Designed analog-integrated circuits for automotive applications, including band-gap circuitry, oscillator, voltage monitor, power supply unit, driver and fail-monitoring circuitry.
• Worked with team on multimillion-dollar projects and delivered on time.
• Interacted with customers to address needs and define design specifications.
• Determined design approaches and circuit topology.
• Verified design approach through simulation.
• Reviewed IC layout and evaluation-board design.
• Defined test procedure for Automatic Test Equipment (ATE), analyzed ATE test results, and resolved issues in test program.
• Evaluated fabricated parts to verify if design target was met.
• Enhanced voltage-monitoring circuit accuracy from 6% to 3%
• Increased reference circuit performance by introducing temperature coefficient trim and using optimized reference topology.

Analog Design Engineer

Designed board-level analog circuits for aviation headsets using operational amplifiers, transistors, and voltage
regulator circuits using electronic SPICE tools.

• Designed active noise reduction circuits using operational amplifiers, transistors, filters, voltage
• Troubleshot and fixed headsets for oscillation issues and crosstalk problems without production
• Used pad layout tools to verify board layouts for headsets and microphone amplifiers.
• Modeled and simulated active noise reduction circuits for aviation headsets using workbench SPICE

Analog Design Engineer

First of three engineers hired to start up a new company division in the United States. Previously, all engineering, marketing, and support was provided overseas at the company's home office. An existing two subscriber line product was having problems with lightning surge damage and needed a cost reduction to stay competitive in the market.

• First "test" assignment was a cost reduction of the existing two subscriber line product. The product had already been through two previous cost reductions by the home office overseas. Reduced the cost of the product by 6%, which increased the corporate annual net profit by approximately $450,000 (1996).
• Redesigned and improved the lightning surge protection on the cost reduced model. One very large customer was having problems with lightning damaged units and was looking for a reason to drop ECI Telecom as a preferred provider. As a test and without prior notification, they required all approved vendor models to pass a 20,000 V, 1000 Amp lightning surge test. The new units survived without damage and ECI Telecom remained a preferred vendor, saving the company over $1,000,000 in annual sales.
• Design team developed an eight analog telephone subscriber line provision for the customer access loop using a single telephone line twisted copper pair carrying DC power and HDSL digital subscriber line technology. Analog design included 5 REN ring generator, analog subscriber line and exchange line interface circuits (FXO and FXS), Built-in-Test (BIT) functionality, and on-board custom PWM power supply design, as well as low noise PWB layout for exceptional bit-error-rate (BER) performance.
• Telecom ISDN and digital subscriber line (DSL, HDSL, ADSL) modems and transmission over twisted copper pair; telecom digital loop carrier (DLC) per Bellcore TR-NWT-000057 specifications; extensive knowledge of access loop telecom circuits, subscriber line and exchange line interface circuits including transmission, signaling, and supervision. Included PWM Power supply design and on-premises ring generator circuit design.
• Design for EMC/EMI compliance for lightning surge, AC power fault, radiated RF emissions, conducted emissions, radiated RF immunity, conducted immunity, electrostatic discharge (ESD), and electrical safety per Bellcore GR-1089-CORE (NEBS) / Telcordia 1089; FCC Part 15 radiated RF emissions; UL 1459 and UL 1950; and IEEE 801-1, 801-2, 801-3, 801-4. Experience includes design and debugging to the component and PCB layout level. Participated in board-level debugging to successfully bring products into compliance
• Designed a low cost, pulse-width modulated switching amplifier ringing generator amplifier capable of driving 15 ringer equivalent (REN) loads, with overload compression and protection. Circuit provided bi-directional power flow for greatest efficiency.

Analog Design Engineer

Work as analog IC design engineer in Freescale Analog Mixed-signal Product design center. The team's projects include high-performance customized IC design using a BiCMOS process. In the following projects, I am responsible for block architecture research & development, transistor-level circuit design, analog blocks and subsystems design from specification, transistor-level simulation, layout verification to final implementation into silicon production, and silicon chip testing.

• Automotive Gyroscope System (Freescale Miranda IP development project)
• High-Performance electronic control system for automotive ESP (Electronic Stability Program) and ABS (Anti-Lock Break System) systems.
• High-Performance power management IC chip for automotive power-train system.

Analog Design Engineer

Developed Verilog model for CTLE Block: The frequency response of continuous time linear equilizer block, a part of SerDes, is modeled using System Verilog language for various modes and equalization settings.

• Designed a Serializer: The Serializer block is designed to serialize 8 bit data at 500MHz clock speed. It implements a simple tree structure. The design is highly area and power optimized.
• Verified a CTLE Block: This block has been verified through Spectre simulations for various modes and equalization settings for the correct functionality as prescribed by the designer of the block
• Designed a high speed Divider Block: The high speed divider sits in the feedback path of a PLL whose VCO works in the range of 3-6GHz supporting up to 7GHz speed and division ratios between 28 and 64. Uses TSMC 28nm technology. It involves high speed design techniques - delay minimization, meeting timing requirements, critical paths.
• Designed a RTC (Real Time Clock): Designed an ultra-low power 32.768 KHz Real Time Clock Oscillator (RTC) IP. It contains a gain stage and crystal oscillator in a loop.
• Designed and Laid out a Band Gap Circuit: Designed and laid out current mode band gap circuit in TSMC 45nm CMOS technology.
• Developed a Verilog Model of a high speed SERDES: Worked on developing a Verilog/System Verilog model for a high speed SerDes transceiver in 28nm technology. It involved developing models for Tx, Rx, bias, PLLs, Tx_equilizer, Rx_equilizer, clock and data recovery, VCOs, filters, phase detectors, high speed feedback divider blocks. This work required me to gain the entire macro level understanding of SerDes to be able to communicate with the digital designers and at the same time transistor level understanding of all the blocks of SerDes to be able to model them. Implementing complex analog circuit behavior - equalization in frequency domain, integration functionality, filters, VCOs, etc, in System Verilog language is extremely challenging.